While operating frequencies of many devices in intelligent electronic systems continually increase in response to demands for greater computational power, avoiding high frequency clocks may be prudent in some circumstances. For example, a low frequency clock may be appropriate in a power consumption sensitive application since power dissipation can be reduced by using lower frequencies. Unfortunately, low frequency operation delivers low performance and thus is typically either limited to periods when performance is secondary to power consumption or to functions which are not computationally intensive.
Serial buses performing system management functions are prime candidates for low frequency operation. Such serial buses are employed in computer systems and other intelligent electronic devices such as audio equipment, video equipment, smart batteries, and smart battery chargers. Generally, these buses transmit system control commands and data between various devices on the bus at relatively low frequencies (e.g., 10-100 kHZ).
Some well known serial buses are the Inter-Integrated Circuit (I.sup.2 C) Bus, the ACCESS.bus, and the System Management Bus (SMBus). The I.sup.2 C bus was developed by Philips Corporation. The ACCESS.bus, an open industry standard which evolved from I.sup.2 C technology, provides a low-cost serial bus allowing control of various computer system devices and internal resources. The ACCESS.bus specification more fully describes the ACCESS.bus and is available from the ACCESS.bus Industry Group in Sunnyvale, Calif.
The ACCESS.bus now also supports the features of another similar serial bus, the SMBus. The SMBus aims to provide intelligent computer system power management by allowing two-way communication for attached devices. For example, intelligent batteries notify users of remaining power and charge requirements and send warnings before failure. Users or system software can respond by adjusting levels of power consumption. Further details of the SMBus are documented in the System Management Bus Specification available from Intel Corporation of Santa Clara, Calif.
Whether attached to an I.sup.2 C bus, an ACCESS.bus, a SMBus, or other bus, devices generally fall into the general categories of master, slave, and host. A device which gains control of the bus and transmits information is a master device. The master device drives a bus clock signal which functions as a strobe, allowing data to be transferred when the bus clock is driven to a low logic level. An open drain driver for the bus clock signal allows other devices to hold the clock signal at this logic level after the master has released it, thereby extending the time available to sample data driven on the bus. The open drain nature of the clock signal does not allow stretching of other events such as start and stop events because they occur when the bus clock is at a high logic level.
A device receiving the transmitted information and potentially stretching the bus clock signal is referred to as a slave device. Each device may have master and slave capabilities, or may remain exclusively a slave device. A serial bus also typically has one host device which communicates with a central processor. This host device has an associated slave port and slave controller allowing the host device to receive commands from other devices on the serial bus. For example, a SMBus host device may receive, from a smart battery, a command to awaken the computer system from a low power suspend mode.
Such data transmissions are generally constrained to a specified frequency range or a specified maximum frequency. Each bus master operates within the specified parameters but transfers data sequences according to its own operating frequency. Thus, in order to maintain compatibility with all possible bus masters, slave devices must be able interpret data sequences that may vary in frequency up to the specified maximum bus frequency.
As a consequence, prior art devices implement slave controller circuits using synchronous logic capable of interpreting signals at the specified maximum frequency. This requires a sampling frequency of at least the rate of information transfer, thus forcing prior art controllers to have an operating frequency at or above the maximum frequency expected to be encountered on the bus.
This operating frequency limitation presents a significant barrier to power conservation, one of the primary goals of serial buses such as the SMBus. The frequency limitation also reduces hardware flexibility by limiting the choice of clocks suitable for clocking slave controller logic. In sum, prior art serial bus interface logic requires high operational frequencies causing additional power consumption and precluding hardware efficiencies which may otherwise be achieved through the use of existing clock signals.